Data processing systems frequently have a cache memory for improving performance. The cache memory is typically used to provide very quick access to instructions which are the ones being most frequently used.
The cache memory is typically in close proximity to a processing unit of the data processing system and has a relatively fast access time. The instructions which are being frequently used are advantageously stored there to improve overall system speed. These same instructions stored in the cache memory are also available elsewhere in the system and accessible via a common bus. The common bus is typically available to a user. When an instruction is fetched in the cache memory, it is desirable, although not necessary, to prevent this address which accessed the instruction in the cache memory from also reaching the common bus. This is desirable because system speed can be increased by not wasting time on the common bus with a redundant address. Consequently, data processors have been developed which prevent an address which accesses a location in cache memory from reaching the common bus. This has the effect of preventing a user from being able to discern an instruction which has been accessed in cache memory.
Being able to discern the sequence of instructions is necessary for a user who is experimenting with a program in microcode whether such experimentation is pursuant to creating or altering a program. Consequently, it has been found useful to provide the microcode programmer with the ability to force all of the instructions onto the common bus where they can be read. Such ability has been available only with software instructions, i.e., in order to achieve this result it has been necessary to place such a command into the program itself. In order to change the timing of such features, the program must be changed. Also because the timing of the feature is in the program, it is not easily tied directly to bus cycles or some other real time measurement.